Design of a Sequential Logic Cell Using LEAP: Layout Design Through Error Aware Transistor Positioning


Year: 
2010
Presenter: 
Full Citation: 
Lee, H.-H. K., K. Lilja, M. Bounasser, P. Relangi, I. R. Linscott, U. S. Inan and S. Mitra (2010), Design of a Sequential Logic Cell Using LEAP: Layout Design Through Error Aware Transistor Positioning, Oral presentation at 2010 IEEE Workshop on Silicon Errors in Logic - System Effects; Stanford, CA; Abstract V-2; 23-24 March, 2010.